The present invention relates to semiconductor bipolar devices, and more particularly to a silicon germanium (SiGe) bipolar transistor having improved electrostatic discharge (ESD) robustness.
Significant growth in both high-frequency wired and wireless markets has introduced new opportunities where compound semiconductors have unique advantages over bulk complementary metal oxide semiconductor (CMOS) technology. With the rapid advancement of epitaxial-layer pseudomorphic SiGe deposition processes, epitaxial-base SiGe heterojunction bipolar transistors have been integrated with main stream advanced CMOS development for wide market acceptance, providing the advantages of SiGe technology for analog and radio frequency (RF) circuitry while maintaining the full utilization of the advanced CMOS technology base for digital logic circuitry.
SiGe heterojunction bipolar transistor devices are replacing silicon bipolar junction devices as the primary element in all analog applications. With increased volume and growth in the applications that use SiGe heterojunction bipolar transistors for external circuitry, ESD robustness is needed. This is especially the case in RF applications such as mobile phone use, where high-transistor speeds and high-frequency responses are needed. As the frequency responses of such devices increase, the loading effect on the transistor, which may lead to excessive noise and distortion, also increases.
Presently, there are few SiGe heterojunction bipolar transistors for use in RF applications and other applications which require high-operating speeds and high frequencies that have satisfactory ESD robustness. In such devices, the base is typically connected to an external pad and is thus vulnerable to both positive and negative HBM pulses.
A typical prior art SiGe heterojunction bipolar transistor is shown, for example, in FIG. 1. Specifically, the structure shown in FIG. 1 comprises semiconductor substrate 10 having subcollector region 14 formed thereon. Isolation regions 12, collector region 16 and pedestal implant region 17 are formed in a Si-containing layer that is formed atop subcollector region 14.
The illustrated prior art structure also includes SiGe layer 18 which includes polycrystalline regions 18b abutting a single-crystal region 18a. The polycrystalline regions are formed predominately over the isolation regions, whereas the single-crystal region is formed over the collector region. Note the dotted lines (labeled as 20) in SiGe layer 18 represent the facet region of the SiGe layer. The facet region is the boundary region wherein the SiGe layer changes from polycrystalline to single-crystal. As one skilled in the art is aware, the facet region may vary somewhat from the drawings of the present invention. For example, facet region 20 may be directed towards or away from the emitter. Note also that a portion of the SiGe layer and the Si-containing layer atop the subcollector include extrinsic base implant regions 23.
The prior art structure also includes patterned insulator 22 formed on SiGe layer 18, the patterned insulator has an opening which exposes portions of the single-crystal SiGe region. Doped polysilicon 24 is then formed on said patterned insulator and is in contact with the single-crystal SiGe region through the above-mentioned opening. The structure also includes silicide regions 28 that are formed on the SiGe layer and in contact with the polysilicon emitter source edge. Note during the annealing step used in forming the silicide regions, emitter diffusion region 26 is formed in the single-crystal SiGe region. Due to the encroachment between the silicide regions and the emitter junction (i.e., polysilicon region 24), the device may suffer from ESD damage.
In view of the above problems with prior art SiGe heterojunction bipolar transistors, there is a continued need for fabricating new and improved SiGe heterojunction bipolar transistors that do not significantly suffer from ESD damage.
One object of the present invention is to provide an ESD robust semiconductor heterojunction bipolar transistor that is capable of operating efficiently at high-operating speeds and high frequencies.
Another object of the present invention is to provide an ESD robust semiconductor heterojunction bipolar transistor that has a low-base resistance thereby improving the performance of the device.
A further object of the present invention is to provide an ESD robust semiconductor heterojunction bipolar transistor in which the salicide regions are moved farther away from the base-emitter junction area and farther away from the facet transition between emitter polysilicon and single-crystal edge.
A yet further object of the present invention is to provide an ESD robust semiconductor heterojunction bipolar transistor that does not include additional ballasting resistor elements.
These and other objects and advantages are achieved in the present invention by using the emitter polysilicon shape to move the salicide edge from the region of the emitter-base junction and farther away from the extrinsic-base implant xe2x80x9clink-resistancexe2x80x9d edge. The extrinsic base is defined herein as the base region prior to the facet.
In one embodiment of the present invention, a semiconductor structure is provided that comprises:
a bipolar transistor comprising a lightly doped intrinsic base;
a heavily doped extrinsic base adjacent to said intrinsic base, a heavily doped/lightly doped base doping transition edge therebetween, said heavily doped/lightly doped base doping transition edge defined by an edge of a window; and
a silicide region extending on said extrinsic base, wherein said silicide region is completely outside said window.
The term xe2x80x9clightly doped intrinsic basexe2x80x9d denotes a base region that is doped with an ion using a dopant dosage of from about 1E11 cmxe2x88x922 to about 1E14 cmxe2x88x922. More preferably, the lightly doped intrinsic base is doped using a dopant dosage of about 1E13 cmxe2x88x922 so that a concentration of about 1E19 cmxe2x88x923 is obtained.
The term xe2x80x9cheavily doped extrinsic basexe2x80x9d denotes a base region that is doped with an ion using a dopant dosage of from about 1E15 cmxe2x88x922 to about 1E16 cmxe2x88x922. More preferably, the heavily doped extrinsic base is doped using a dopant dosage of about 1E15 cmxe2x88x922 so that a concentration of about 1E20 cmxe2x88x923 is obtained.
In another embodiment of the present invention, the inventive semiconductor structure comprises:
a bipolar transistor comprising an extrinsic base having a polycrystalline/single crystal facet; and
a silicide region on said extrinsic base, wherein said silicide region extends extensively on said polycrystalline side of said facet.
In yet another embodiment of the present invention, the semiconductor structure comprises:
a bipolar transistor comprising an emitter;
an isolation surrounding said emitter, said isolation having an inner edge;
an extrinsic base extending on said isolation; and
a silicide region on said extrinsic base, wherein said silicide region extends exclusively outside said inner edge.
In a further embodiment of the present invention, a semiconductor heterojunction bipolar transistor structure is provided that comprises:
a substrate of a first conductivity-type having a subcollector of a second conductivity-type present therein, said substrate including isolation regions formed atop said subcollector;
a SiGe-containing layer formed on said substrate including said isolation regions, wherein said SiGe-containing layer comprises a single-crystal SiGe-containing region abutted by polycrystalline SiGe-containing regions, said single-crystal and polycrystalline regions are separated by a facet region;
a patterned emitter formed on said SiGe-containing layer, said patterned emitter including an insulator, doped polysilicon and an emitter diffusion region; and
metal salicide regions formed on said polycrystalline SiGe-containing regions above said isolation regions, wherein said metal salicide regions are displaced from said facet region and from said emitter diffusion region.
In one embodiment of the present invention, the patterned emitter (i.e., patterned doped polysilicon and insulator) extends beyond the edges of the isolation regions. In yet other embodiment of the present invention, the patterned emitter is not formed over any portion of the isolation regions.
The present invention is also directed to a method for providing the above-described structure. Specifically, the method of the present invention includes the steps of:
(a) forming a SiGe-containing film on a surface of a structure which includes at least a subcollector region, said SiGe-containing film comprises a single-crystal SiGe-containing region abutted by polycrystalline SiGe-containing regions, said single-crystal and polycrystalline regions are separated by a facet region;
(b) forming an insulator on said SiGe-containing film;
(c) providing an opening in said insulator so as to expose a portion of said single-crystal SiGe-containing region;
(d) forming a doped polysilicon layer over the insulator including in said opening so as to cover said exposed portion of said single-crystal SiGe-containing region;
(e) patterning said doped polysilicon layer and said insulator so as to at least expose portions of said polycrystalline SiGe-containing regions that are formed on said isolation regions; and
(f) saliciding said exposed portions of said polycrystalline SiGe-containing regions above said isolation regions forming a metal salicide region therein, wherein during said saliciding dopant from said doped polysilicon diffusions into the single-crystal region forming an emitter diffusion region, and wherein each of said metal salicide regions is displaced from said facet region and from said emitter diffusion region.
In one embodiment, the patterning step forms an emitter region in which the doped polysilicon extends beyond the edges of the isolation regions. In other embodiment of the present invention, the patterning step forms an emitter region in which the doped polysilicon does not extend over any portion of the isolation regions. In this embodiment, the emitter polysilicon is not in contact with the metal salicide regions.